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RENESAS LSIs
M5M5256DFP,VP -70G,-70GI,-70XG
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5256DFP,VP is 262,144-bit CMOS static RAMs organized as 32,768-words by 8-bits which is f abricated using high-perf ormance 3 poly silicon CMOS technology . The use of resistiv e load NMOS cells and CMOS periphery results in a high density and low power static RAM. Stand-by current is small enough f or battery back-up application. It is ideal f or the memory sy stems which require simple interf ace. Especially the M5M5256DVP are packaged in a 28-pin thin small outline package.
PIN CONFIGURATION (TOP VIEW)
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2
1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26
Vcc /W
A13 A8 24 A9 23 A11 22 /OE
25 21 20
19 18 17 16 15
FEATURE
Ty pe Power supply current Access Oprating time Temperature Activ e Stand-by (max) (max) (max) 20A M5M5256DFP,VP -70G
(Vcc= 5.5V)
DQ3 GND 14
A10 /S DQ8 DQ7 DQ6 DQ5 DQ4
Outline 28P2W-C (FP)
70ns
0~70C
12A
(Vcc= 3.6V)
22 /OE 23 A11 24 25 26 27 28 1 2 3 4 5 6 7
45mA
(Vcc= 5.5V)
40A
(Vcc= 5.5V)
M5M5256DFP,VP -70GI
70ns
-40~85C
24A 25mA
(Vcc= 3.6V) (Vcc= 3.6V)
5A M5M5256DFP,VP -70XG 70ns
(Vcc= 5.5V)
0~70C
2.4A
(Vcc= 3.6V)
0.05A
(Vcc= 3.0V Typical)
*Single 3.0~5.5V power supply *No clocks, no ref resh *Data-Hold on +2.0V power supply *Directly TTL compatible : all inputs and outputs *Three-state outputs : OR-tie capability */OE prev ents data contention in the I/O bus *Common Data I/O *Battery backup capability *Low stand-by current .......... 0.05A(ty p.)
A9 A8 A13 /W Vcc A14 A12 A7 A6 A5 A4 A3
M5M5256DVP
A10 21 /S 20 DQ8 19 DQ7 18 DQ6 17 DQ5 16 DQ4 15 GND 14 DQ3 13 DQ2 12 DQ1 11 A0 10 A1 9 A2 8
Outline
28P2C-A (VP)
PACKAGE
M5M5256DFP M5M5256DVP : 28 pin 450 mil SOP 2 : 28pin 8 X 13.4 mm TSOP
APPLICATION
Small capacity m emory units
1
RENESAS LSIs
M5M5256DFP,VP -70G,-70GI,-70XG
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
The operation mode of the M5M5256DFP,VP is determined by a combination of the dev ice control inputs /S, /W and /OE. Each mode is summarized in the f unction table. A write cy cle is executed whenev er the low lev el /W ov erlaps with the low lev el /S. The address must be set up bef ore the write cy cle and must be stable during the entire cy cle. The data is latched into a cell on the trailing edge of /W, /S, whichev er occurs f irst, requiring the setup and hold time relativ e to these edge to be maintained. The output enable /OE directly controls the output stage. Setting the /OE at a high lev el,the output stage is in a high-impedance state, and the data bus contention problem in the write cy cle is eliminated.
A read cy cle is executed by setting /W at a high lev el and /OE at a low lev el while /S are in an activ e state. When setting /S at a high lev el, the chip is in a nonselectable mode in which both reading and writing are disabled. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips and memory expansion by /S. The power supply current is reduced as low as the stand-by current which is specif ied as Icc3 or Icc4, and the memory data can be held at +2V power supply , enabling battery back-up operation during power f ailure or power-down operation in the nonselected mode.
FUNCTION TABLE
/S H L L /W X L H /OE X X L Mode Non selection Write Read DQ High-impedance DIN DOUT Icc Stand-by Activ e Activ e
High-impedance Activ e L H H Note * "H" and "L" in this table mean VIH and VIL, respectiv ely . * "X" in this table should be "H" or "L".
BLOCK DIAGRAM
A8 A 13 A 14 A 12 A7 A6 A5 A4 ADDRESS INPUT A3 25 26 1 2 2 3 4 5 6 7 (512 ROWS X 17 512 COLUMNS) 18 19 32768 WORD X 8BIT
11 12 13 15 16
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DATA I/O
A2 A1 A0 A 10 A 11 A9 WRITE CONTROL INPUT /W CHIP SELECT INPUT /S
8 9 10 21 23 24 CLOCK GENERATOR
27 20
28 14
VCC (5V) GND (0V)
OUTPUT ENABLE /OE INPUT
22
2
RENESAS LSIs
M5M5256DFP,VP -70G,-70GI,-70XG
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply voltage Vcc VI Input voltage Output voltage VO Pd Power dissipation Topr Tstg Operating temperature Storage temperature Conditions With respect to GND Ta=25C -G,-XG -GI Ratings -0.3*~7.0 -0.3*~Vcc+0.3
(Max 7.0)
Unit V V V mW
C C
0~Vcc 700 0~70 -40~85 -65~150
_ * -3.0V in case of AC ( Pulse width < 30ns )
DC ELECTRICAL CHARACTERISTICS
Limits1 Symbol Parameter VIH VIL VOH1 VOH2 VOL II IO Icc1 High-level input voltage Low-level input voltage High-level output voltage 1 IOH=-1mA IOH=-0.5mA IOH=-0.1mA High-level output voltage 2 IOH=-0.05mA IOL=2mA Low-level output voltage IOL=1mA Input current Output current in off-state Active supply current
(AC, MOS lev el )
Limits2
(Vcc=5.00.5V)
Vcc +0.3
Test conditions
(Vcc=3.30.3V)
Vcc +0.3
Unit V V V V
Min Typ Max Min Typ Max 2.0 -0.3* (Vcc=5.00.5V) (Vcc=3.30.3V) (Vcc=5.00.5V) (Vcc=3.30.3V) (Vcc=5.00.5V) (Vcc=3.30.3V) 2.4
Vcc -0.5
2.2
0.6 -0.3* 2.4
Vcc -0.5
0.8
0.4 1 1 13 1.5 14 1.5 25 3 25 3 1.2 3.6 0.8 12 2.4 24 0.33 25 2 25 4
0.4 1 1 40 4 45 8 2 6 1.2 20 5 40 3
V A A mA mA
VI=0~Vcc /S=VIH or or /OE=VIH, VI/O=0~Vcc
_ /S<0.2V, Output-open
Other inputs<0.2V or >Vcc-0.2V /S=VIL, Output-open other inputs=VIH or VIL ~25C
70ns 1MHz 70ns 1MHz -G,-GI -XG
Icc2
Active supply current
(AC, TTL lev el )
0.05 0.3
0.1 0.4 A
Icc3
Stand-by current
-G,-GI _ /S>Vcc-0.2V, ~40C -XG other inputs =0~Vcc -G,-GI ~70C -XG ~85C -GI /S=VIH,other inputs=0~Vcc
Icc4
Stand-by current
mA
* -3.0V in case of AC ( Pulse width _ 30ns ) <
CAPACITANCE
Symbol CI CO Parameter Input capacitance Output capacitance Test conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz Min Limits Typ Max 6 8 Unit pF pF
Note 0: Direction f or current f lowing into an IC is positiv e (no mark). 1: Ty pical v alue is one at Ta = 25C. 2: CI, CO are periodically sampled and are not 100% tested.
3
RENESAS LSIs
M5M5256DFP,VP -70G,-70GI,-70XG
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE
Limits1 Symbol tCR ta(A) ta(S) ta(OE) tdis(S) tdis(OE) ten(S) ten(OE) tV(A) Parameter Read cycle time Address access time Chip select access time Output enable access time Output disable time after /S high Output disable time after /OE high Output enable time after /S low Output enable time after /OE low Data valid time after address
Vcc=3.30.3V
Limits2
Vcc=5.00.5V
Unit ns ns ns ns ns ns ns ns ns
Min 70
Max 70 70 35 25 25
Min 70
Max 70 70 35 25 25
5 5 10
5 5 10
(2) WRITE CYCLE
Limits1 Symbol Parameter
Vcc=3.30.3V
Limits2
Vcc=5.00.5V
tCW Write cycle time tw(W) Write pulse width tsu(A) Address setup time tsu(A-WH) Address setup time with respect to /W high tsu(S) Chip select setup time tsu(D) Data setup time th(D) Data hold time trec(W) Write recovery time tdis(W) Output disable time from /W low tdis(OE) Output disable time from /OE high ten(W) Output enable time from /W high ten(OE) Output enable time from /OE low
Min 70 55 0 65 65 30 0 0 5 5
Max
Min 70 50 0 65 65 30 0 0 5 5
Max
Unit ns ns ns ns ns ns ns ns ns ns ns ns
25 25
25 25
4
RENESAS LSIs
M5M5256DFP,VP -70G,-70GI,-70XG
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
(3) TIMING DIAGRAMS Read cycle
A0~14 ta(A) ta (S) /S
(Note 3)
tCR
tv (A)
ta (OE) ten (OE)
tdis(S)
(Note 3)
/OE
(Note 3)
tdis (OE) ten (S)
(Note 3)
DQ1~8
/W = "H" lev el
DATA VALID
Write cycle (/W control mode)
A0~14
tCW
tsu (S) /S
(Note 3) (Note 3)
tsu (A-WH) /OE tsu (A) /W tdis (W) tdis (OE) DQ1~8
(Note 3)
tw (W)
trec (W)
ten (W)
ten(OE)
DATA IN STABLE (Note 3)
tsu (D)
th (D)
5
RENESAS LSIs
M5M5256DFP,VP -70G,-70GI,-70XG
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle ( /S control mode)
tCW A0~14 tsu (A) /S
(Note 5)
tsu (S)
trec (W)
/W
(Note 3)
(Note 4)
tsu (D)
th (D)
(Note 3)
DQ1~8
DATA IN STABLE
(4) MEASUREMENT CONDITIONS
Limits1:Vcc=3.30.3V Input pulse level .............. VIH=2.4V,VIL=0.4V Input rise and fall time ..... 5ns Reference level ................ VOH=VOL=1.5V Output load ...................... Fig.1, CL=30pF CL=5pF (for ten,tdis) Transition is measured 500mV from steady state voltage. (for ten,tdis)
DQ CL
(Including scope and JIG)
Fig.1 Output load
Limits2:Vcc=5.00.5V Input pulse level .............. VIH=2.4V,VIL=0.6V Input rise and fall time ..... 5ns Reference level ................ VOH=VOL=1.5V Output load ...................... Fig.2, CL=100pF CL=5pF (for ten,tdis) Transition is measured 500mV from steady state voltage. (for ten,tdis)
Note 3 4 5 6 7 : : : : :
Vcc 1.8k DQ 990
(Including scope and JIG)
CL
Fig.2 Output load
Hatching indicates the state is "don't care". Writing is executed in ov erlap of /S and /W low. If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state. Don't apply inv erted phase signal externally when DQ pin is output mode. ten, tdis are periodically sampled and are not 100% tested.
6
RENESAS LSIs
M5M5256DFP,VP -70G,-70GI,-70XG
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS
Symbol
Vcc (PD) VI (/S)
Parameter
Power down supply v oltage Chip select input /S
Test conditions
_ 2.2V < VCC(PD) _ _ 2V< VCC(PD) < 2.2V
Min 2 2.2
Limits Typ Max
Unit
V V
VCC(PD)
V
~25C
Icc _ Vcc = 3V,/S > Vcc-0.2V, Other inputs=0~Vcc
-G,-GI -XG -G,-GI -XG -G,-GI -XG -GI 0.05
1 0.2 3 0.6 10 2 20 A
(PD)
Power down supply current
~40C ~70C ~85C
(2) TIMING REQUIREMENTS
Symbol tsu (PD) trec (PD) Parameter
Power down set up time Power down recov ery time
Test conditions
Min
0
Limits Typ Max
Unit
ns ns
tCR
(3) POWER DOWN CHARACTERISTICS /S control mode
Vcc tsu (PD)
2.2V 3.0V 3.0V
trec (PD)
2.2V
/S
_ /S > Vcc-0.2V
7
RENESAS LSIs
M5M5256DFP,VP -70G,-70GI,-70XG
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
Nippon Bldg.,6-2,Otemachi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan
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Notes regarding these materials
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